Integrated circuit (IC) chips are often electrically connected by wires (e.g., gold or aluminum wires) to a package substrate in a packaging assembly to provide external signal exchange. Such wires are typically wire bonded to bond pads formed on an IC chip using thermal compression and/or ultrasonic vibration. A wire bonding process exerts thermal and mechanical stresses on a bond pad and on the underlying layers and structure below the bond pad. The bond pad structure needs to be able to sustain these stresses to ensure a good bonding of the wire.
Prior bond pad structures were fabricated from the bottom layer to the top layers, which did not allow metal wiring circuitry and semiconductor devices to pass under, or be located below, the bond pad structure. FIG. 1 illustrates a conventional wire bond pad structure. An interconnect structure 4 is formed on a semiconductor substrate 2. A passivation layer 6 is formed on the top metallization layer of the interconnect structure 4. A bond pad 8 is formed on the passivation layer 6. Bond pad 8 is electrically connected to metal lines 10 in the top metallization layer. A passivation pad 12, which is a portion of the passivation layer 6, remains under the bond pad 8. This structure is typically referred to as a bond-on-passivation structure since wires will be bonded to the bond pad, which is on the passivation pad 12. With the insulation of passivation pad 12, copper lines 14 can be formed in the top metallization layer.
In conventional integrated circuit structures such as the one shown in FIG. 1, the substrate regions under the bond pad 8 have no active devices formed in them, so that stresses applied to the active devices during bonding processes will not be applied directly on the active devices. For a more efficient use of chip area or to reduce the chip size, it is desirable to form semiconductor devices and metal wiring circuitry under the bond pad. This is sometimes referred to as bond over active circuits (BOAC). At the same time, many processes now use low-k and ultra low-k dielectric materials for the inter-metal dielectric (IMD) layers to reduce RC delay and parasitic capacitances. The general trend in IMD designs is that the dielectric constant (k) tends to decrease from the top downward toward the substrate.
However, as the dielectric constant (k) decreases, as a general rule, the strength of the dielectric material decreases. Hence, many low-k dielectric materials are highly susceptible to cracking or lack the strength needed to withstand some mechanical processes (e.g., wire bonding, CMP). Thus, a need exists for a bond pad structure that can sustain and better disperse the stresses exerted on it by a wire bonding process, that is compatible with the use of low-k dielectric materials for inter-metal dielectric layers, and that will also allow circuitry and devices to be formed under the bond pad.